1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device including a power metal oxide silicon field effect transistor.
2. Description of the Related Art
A power metal oxide silicon field effect transistor (MOSFET) has been widely used recently because it can drive a large load at a high speed.
A circuit diagram illustrating a conventional semiconductor device is in FIG. 6.
As shown in FIG. 6, the conventional semiconductor device is constituted by an input signal source 9 for generating an input signal, a current limiting resistor 10 for limiting electric current flowing through the device, a power supply 13, a load 14, a power MOSFET 12 for controlling the supply of current to the load 14, a constant-voltage diode 25, a diode 26, and a control circuit 17 for controlling the operation of the power MOSFET 12; provided in the control circuit 17 and connected in parallel between an input terminal 3 and a GND terminal 16 are a resistor 1 and a constant-voltage diode 2, resistors 4 and 5, a comparator 6 for performing comparison of the value of the voltage which has undergone the division through the resistors 4, 5, and a P channel (Pch) MOSFET 7 and an N channel (Nch) MOSFET 8 in which the outputs from the comparator 6 are applied to the gate terminals thereof, a resistor 11 also being included in the control circuit 17, which resistor 11 has one end thereof connected to the drain terminals of the PchMOSFET 7 and NchMOSFET 8 and the other end thereof connected to the gate terminal of the power MOSFET 12; and there is also included a parasitic NPN bipolar transistor 24 having an emitter terminal thereof connected to the input terminal 3 and a collector terminal thereof connected to an output terminal 15.
FIG. 7 is a cross-sectional view showing the structure of the semiconductor device illustrated in FIG. 6.
As shown in FIG. 7, the conventional semiconductor device is comprised of an N.sup.+ substrate 21 serving as the output of the power MOSFET 12, a P.sup.- semiconductor layer 22 joined onto the N.sup.+ substrate 21, and an N.sup.- semiconductor layer 23 which is joined onto the P.sup.- semiconductor layer 22 and which has the control circuit 17.
The operation of the semiconductor device configured as described above will now be described.
FIG. 8 illustrates the operation of the semiconductor device shown in FIG. 6 and FIG. 7; (a) shows the voltage of a signal output from the input signal source 9 and the voltage value at the input terminal 3, (b) illustrates the output voltage of the comparator 6, (c) illustrates the gate voltage of the power MOSFET 12, and (d) illustrates the voltage value and the current value at the output terminal 15.
When the voltage output from the input signal source 9 rises and when the value of the voltage, which has undergone the division through the resistors 4 and 5, exceeds the constant voltage of the constant-voltage diode 2 (t1) via PchMOSFET 7, the output of the comparator 6 switches to a low level.
This turns the PchMOSFET 7 ON and turns the NchMOSFET 8 OFF.
Thus, electric charge is accumulated at the gate of the power MOSFET 12 and the power MOSFET 12 is placed in an ON state, causing electric current to flow into the load 14.
Next, the voltage output from the input signal source 9 lowers and when the value of the voltage, which has undergone the division through the resistors 4 and 5, goes down to the constant voltage of the constant-voltage diode 2 or lower (t2) via Nch MOSFET 8, the output of the comparator 6 switches to a high level.
Then the PchMOSFET 7 turns OFF, whereas the NchMOSFET 8 turns ON.
This causes the electric charge, which has been accumulated at the gate of the power MOSFET 12, to be discharged, and the power MOSFET 12 is changed to an OFF state.
And the reactance component of the load 14 leads to a rise in the voltage at the output terminal 15, and when the voltage at the output terminal 15 exceeds the constant voltage value of the constant-voltage diode 25, electric current flows from the NchMOSFET 8 to the GND terminal 16 or from the drain of the PchMOSFET 7 to the input terminal 3 through the constant-voltage diode 25, the diode 26, and the resistor 11.
This in turn causes the gate voltage of the power MOSFET 12 to be continued to be biased; the bias allows electric current to flow into the power MOSFET 12 due to so-called "dynamic clamping."
In the conventional semiconductor device described above, however, the parasitic NPN transistor 24 is actuated whenever the voltage at the input terminal 3 drops below the voltage at the GND terminal 16, posing a problem in that electric current flows from the output terminal 15 to the input terminal 3, damaging the device.
More specifically, as shown in FIG. 7, in the foregoing conventional example, the parasitic NPN transistor 24 is designed so that the N.sup.+ substrate 21 serves as the collector, the P.sup.- semiconductor layer 22 serves as the base, and the N.sup.- semiconductor layer 23 serves as the emitter; therefore, with the voltage applied to the output terminal 15, the voltage at the input terminal 3 becomes lower than the voltage at the GND terminal 16, and when the difference therebetween exceeds the voltage between the base and the emitter to cause electric current to flow from the GND terminal 16 to the input terminal 3, thus undesirable actuating the parasitic NPN transistor 24.
In particular, when a high voltage (e.g. 70 V) is applied to the output terminal 15 in such a case as the dynamic clamping, a second breakdown which is peculiar to a bipolar transistor results with a consequence greater chance of damage to the device.
To cope with the difficulty, a device for protecting a semiconductor device from damage has been disclosed in Japanese Patent Application Laid Open No. Hei 5-58583.
FIG. 9 is a block diagram illustrative of the sketch of the semiconductor device.
As shown in FIG. 9, the device includes a MOSFET 31 having a high threshold voltage V.sub.T connected between the input terminal 3 and the GND terminal 16; when static electricity is applied to the input terminal 3 and when the voltage between the input terminal 3 and the GND terminal 16 exceeds the threshold voltage V.sub.T (approximately 20 to 25 V in this example), the second breakdown results, thus turning the MOSFET 31 ON.
However, the problem in the semiconductor device shown in FIG. 6 is the damage to the device caused by the parasitic NPN transistor 24 which is actuated when the voltage at the input terminal 3 is lower than the voltage at the GND terminal 16; therefore, the publicly known example illustrated in FIG. 9 does not make sense.
There is another publicly known example, namely, "Supply Terminal Protection" of "Reverse-Voltage Protection Methods for CMOS Circuits" (IEEE JOURNAL Vol24, February 1989).
FIG. 10 is a block diagram showing the sketch of the semiconductor device, and FIG. 11 is a cross-sectional view illustrative of the structure of the device shown in FIG. 10.
As shown in FIG. 10 and FIG. 11, the device has a PchMOSFET 34 connected between V.sub.DD 32 and an N substrate 33 to prevent short-circuit current from flowing through a parasitic diode 35 when V.sub.DD &lt;V.sub.SS.
In the semiconductor device shown in FIG. 6, however, since the current limiting resistor 10 is inserted, there is no need to provide preventive measures against short-circuit current even when the V.sub.DD 32 is replaced by the input and the V.sub.SS by GND. Further, mounting the power MOSFET on the device shown in FIG. 10 and FIG. 11 inevitably makes a high voltage-withstand horizontal type power MOSFET which provides an undesirable high ON resistance (e.g. approximately 1.5 times for 70-volt voltage withstand).
The present invention has been accomplished in view of the problems with the prior arts described above, and it is an object of the present invention to provide a semiconductor device which is capable of preventing the damage to the device caused by the undesirable actuation of a parasitic NPN parasitic transistor.